CS501 - Advance Computer Architecture Solution Assignment No 3 Spring 2021

 

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Case:

Consider an Intel processor operating at a frequency of 1 GHz. After an interrupt is generated, the processor takes 1200 clock cycles for context switch to the interrupt handling process and then an additional 15000 clock cycles (Raise For Success) are spent in executing the interrupt service routine (ISR) during an interrupt handling. The processor uses CPU polling technique used to identify the interrupting module. During the time when there is no interrupt, the processor polls (Raise For Success) the devices after every 1ms and each polling takes 400 clock cycles.
Consider the given scenario, answer the following questions:

 

• If 300 interrupt requests are generated per second, then how many cycles per second does the processor spend handling I/O from the device?
• How many cycles per second are spent by the processor in polling the devices?

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Solution: 

1:

15,000+ (Raise For Success) 2*1200
15,000+2400
17,400
Now:
300*17,400 = 5,220,000 cycles per second are spent handling I/O using interrupts.

2:

As we know 1 Ghz CPU time is=1*10⁹

17,400/ (1*10⁹)

=0.000174seconds

=174 microseconds

174 microseconds is equal to 0.174msec.

For 300 interrupt per second:

0.174*300=52.2msec

This leaves 1200-52.2

=1147.8msec for polling

Since the processor polls (Raise For Success) once every 1 MS during the time when there is no interrupt, this corresponds to:

11478/1=1147.8 times per second

The total number of cycles required for polling is:

1147.8*400

=477120 cycles per second.

Thus, the total time spent (Raise For Success) on I/O when using polling with interrupts is:

5,220,000+477120=5697120

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